| 摘要 |
PURPOSE:To realize a high speed operation by constituting a frequency-dividing circuit by means of invertors and D-flip flops. CONSTITUTION:The frequency-dividing circuit is constituted in such a way that a frequency is inverted via a delay of two bits by the D-flip flops DFF 8, DFF 9 in the invertor INV0 and it is returned again to the input of DFF 8. A clock is frequency-divided into 1/4 by the circuit. Since only the invertor INV is inserted between DFF 8 and 9 in the frequency-dividing circuit, the operation speed near the toggle frequency of a flip flop single body can be realized. Thus, the maximum operation speed of the frequency-dividing circuit can be realized. |
