发明名称 SEMICONDUCTOR NON-VOLATILE MEMORY
摘要 <p>PURPOSE:To correspond to the speed up of a write operation by providing a boosting circuit impressing a voltage on the gate of an enhancement-type transistor and a switch circuit impressing the voltage on the gates of depression- type transistors. CONSTITUTION:When a write enable signal WE is in an inactivated state (5V), the output A2 of the switch circuit 10 becomes zero V, the first depression-type transistor 8 is turned off and fine V is impressed on the gate of the second depression type transistor 7. The impression potential Vcc of an input node 2 appears in a switching potential output node 3. When the write enable signal WE is in an activated state (0V), the impression potential Vpp of a switching potential input node 1 appears in the switching potential output node 3 through the enhancement-type transistor 6 and the first depression-type transistor 8. At the time of reading, the boosting circuit 5 does not execute the boosting operation and the enhancement-type transistor 6 comes to an off-state. Thus, correspondence to the write operation can sufficiently be executed.</p>
申请公布号 JPH04141894(A) 申请公布日期 1992.05.15
申请号 JP19900260496 申请日期 1990.10.01
申请人 TOSHIBA CORP 发明人 TANAKA SUMIO
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
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