| 摘要 |
<p>PURPOSE:To shorten bit line charging time by providing an N-channel-type MOS transistor where the outputs of first invertor circuits are set to be gates, the outputs of second invertor circuits to be sources and a drain is set to be power source potential. CONSTITUTION:The N-channel-type MOS transistor N9 where the outputs of the first invertor circuits P2 and N2 are set to be the gates, the outputs of the second invertor circuits P3 and N4 are set to be the sources and the drain is set to be power source potential is provided. When bit line selection lines L1 and L2 are switched and the potential of a node 4 deteriorates, the level of a node 3 is speedily raised to a gate potential level setting the transistor N9 to a large current supply register and therefore the rise of the potential of a node 5 becomes faster. Then, the bit line selection line is switched and charge for a bit line 6 is executed. Thus, bit line charge time can be shortened.</p> |
