| 摘要 |
A tuple of logic interchange signals is generated from the logic input signals as a representation of a logic concatenation. Interchange signals may, for example, be generated via selection from logic intermediate signals prepared therefor. Tuples of interchange signals may be concatenated to form further sets of interchange signals. Circuit components may also be inserted to recognise and correct errors. It is, for instance, possible greatly to increase reliability in accordance with error correction in applications with logic circuit components liable to failure and with a large number of logic components. A tuple of interchange signals may be concatenated with reconstruction signals to generate an output signal. |
