| 摘要 |
<p>PURPOSE:To synchronize a write timing signal and a read timing signal by selecting a latch output and a write data signal according to the control of a write control circuit and reading the read data signal according to the control of a read counter. CONSTITUTION:A write control circuit 105 compares a 1st write address signal 123 with a 2nd write address signal 124 and outputs a control signal 126 for a selector 107 and a control signal 125 for a 2nd write counter 102 so that the write is correctly implemented with the dissidence is detected. The selector 107 selects a write data signal 151 and an output signal 152 of a latch 106 to delay the signal 151 by one time slot according to the control signal 126 and uses the write data signal to a buffer memory 108 as the selector output signal 153. Normally, the write data signal 151 is selected. The 2nd write counter 102 is operated to make write to the buffer memory 108 once per one time slot normally to synchronize the write and read signal with the control signal 125.</p> |
