Random access memory device having transfer gate unit for blocking flush write data buffer unit from parasitic capacitance coupled with bit line pairs of memory cells.

摘要

A dynamic random access memory device enters a flush write phase of operation for writing a flush write data bit into a plurality of random access memory cells (M11 to m1n or Mm1 to Mmn), and the flush write data bit is transferred from a flush write data buffer unit (18) through a transfer gate unit (17), a set of bit line pairs (Bq1 to BQn) respectively coupled with sense amplifier circuits (SA1 to SAn), another transfer gate unit (13) and another set of bit line pairs (BP1 to BPn) coupled with a random access memory cell array (12), wherein another transfer gate unit (13) blocks the flush write data buffer unit and the sense amplifier circuits from parasitic capacitances coupled with another set of bit line pairs (BP1 to BPn) so that the flush write data buffer unit with small current driving capability rapidly produces small differential voltage levels indicative of the flush write data bit on the bit line pairs coupled with the sense amplifier circuits. <IMAGE>