发明名称 PLL CIRCUIT
摘要 PURPOSE:To realize a stable loop gain without a dead band by using the 1st phase comparator of a phase frequency comparison type so as to lock the oscillating frequency of an oscillator up to a prescribed frequency band and locking the oscillated signal to a reference signal through the loop control with the output of the 2nd phase comparator of analog mixer type. CONSTITUTION:This circuit is provided with an oscillator 10, the 1st phase comparator of phase frequency comparison type 23, the 2nd phase comparator of analog mixer type 24, a discrimination circuit 27, a loop filter 50, and switching circuits 46, 51, 52. Thus, when a frequency difference between the reference signal and the output component signal of the oscillator 10 is a prescribed frequency or above, the frequency of the output component signal of the oscillator 10 is locked by the detection output of the 1st phase comparator 23 in a direction where the frequency is close to the frequency of the reference signal. Moreover, when a frequency difference between the reference signal and the output component signal of the oscillator 10 is a prescribed frequency or below, the output component signal of the oscillator 10 is locked to the reference signal by the detection output of the 2nd phase comparator 24. Thus, the stable PLL circuit without a dead band is realized.
申请公布号 JPH04139917(A) 申请公布日期 1992.05.13
申请号 JP19900261873 申请日期 1990.09.29
申请人 ANRITSU CORP 发明人 OTSUKA TOSHIMASA
分类号 H03L7/089;H03L7/087;H03L7/10;H03L7/113 主分类号 H03L7/089
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