Dielectric layers for integrated circuits.

摘要

In an illustrative embodiment, the present invention includes the formation of three dielectric layers (e.g., 21,27,29), one upon another, and the planarizing or etching back of the third layer (e.g., 29). Various embodiments may feature a second sandwiched layer (e.g., 35) which tends to inhibit mobile ion transport from the layer above the second layer (e.g., 37) to the layer (e.g., 21) below the second layer (e.g., 35).