发明名称 DEBUGGING MICROPROCESSOR
摘要 PURPOSE:To shorten the access selecting time by providing two output terminals for DS signals and a selection circuit which decides one of two DS signals that should be validated in a debugging microprocessor. CONSTITUTION:A debugging microprocessor 1 is provided with the output terminals 3 and 4 for two DS signals 6 and 7 serving as a memory to especially receive an access and an I/O access selection circuit and a selection circuit 13 which validates the signal 6 or 7 based on the type of the program under execution or an instruction of the processor 1 and also invalidates the other one of both signals 6 and 7. Thus it is possible to shorten the time needed for decision an access destination in the processor 1 and also to design an in-circuit emulator 2 which has an operation more approximate to an actual microprocessor.
申请公布号 JPH04139538(A) 申请公布日期 1992.05.13
申请号 JP19900264346 申请日期 1990.10.01
申请人 NEC CORP 发明人 KANEKO SHIGEYUKI
分类号 G06F11/28;G06F11/22 主分类号 G06F11/28
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