| 摘要 |
PURPOSE:To unnecessitate forming a load resistance in a memory cell, reduce the area of the memory cell, and realize high integration level and high density, by connecting two Schottky barrier diodes in parallel, and connecting them with the load of a transistor. CONSTITUTION:On a part of an N-type epitaxial layer 3, a platinum silicide layer 7 formed by turning the surface into platinum silicide is formed. On the interface of the layer 7 and the layer 3, a first Schottky barrier diode SBD1 (or SBD3) whose area is 40mum<2> is constituted. A part of a titanium tungsten (TiW) layer 8 formed on the layer 7 is brought into contact with the layer 3 on the periphery of the layer 7. In this contact area, a second Schottky barrier diode SBD2 (or SBD4) whose area is 0.4mum<2> is constituted. 9, 11, 12, and 15 are a Schottky barrier diode electrode, a base electrode, a collector electrode, and an emitter electrode, respectively. A pair of the structures are arranged, and a circuit is constituted by connecting them crosswise. |
