发明名称 ELECTRICAL TESTING JIG FOR SEMICONDUCTOR DEVICE
摘要 PURPOSE:To enable the plating thickness of a bonding pad to be equalized by a method wherein the first through hole connecting to a bonding pad and a testing circuit and the second through hole connecting to a testing pad are made conductive by a pattern in low thermal conductivity while the openings of the through holes are closed with the pattern. CONSTITUTION:The title jig is provided with a conductive pattern 9 in low thermal conductivity on a wiring board provided inside a multilayer board, a bonding pad 2 and the first through hole 4 connecting to the conductive pattern 9 connected to a testing circuit having the opening thereof on the wiring substrate closed with the conductive pattern 9 furthermore, the second through hole 5 connecting to the conductive pattern 9 connected to an electrical testing pad 7 having the opening thereof on the wiring substrate closed with the conductive pattern 9. Through these procedures, the melting down of the soldered part of a bonding pad 2 to be drawn toward the testing pad 7 by surface tension can be avoided also enabling the dispersion in the plating thickness of the bonding pad 2 to be avoided.
申请公布号 JPH04139847(A) 申请公布日期 1992.05.13
申请号 JP19900264376 申请日期 1990.10.01
申请人 NEC CORP 发明人 MORI YOICHI
分类号 H01L21/60;H01L21/66 主分类号 H01L21/60
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