SELF-ALIGNED PROCESS FOR FABRICATING SMALL SIZE DMOS CELLS AND MOS DEVICES OBTAINED BY MEANS OF SAID PROCESS

摘要

Described is an improved fabrication process for vertical DMOS cells contemplating the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, allowing also to form the source region. Opening of the relative contact is also effected by self alignment technique, further simplifying the process.