MECHANISM FOR LOCK-UP FREE CACHE OPERATION WITH A REMOTE ADDRESS TRANSLATION UNIT

摘要

It is known to use a miss information holding register in a cache memory organization to store the details of a CPU load request on a cache miss so that the cache may accept subsequent requests pending the receipt of data in respect of the first request. In the subject invention, this organization is modified for use with a virtual addressable cache memory by incrementing a counter which overflows to free the miss information holding register with each untranslatable response signal from the address translation unit relating to the request stored in the miss information holding register. The modified organization also clears the used bit associated with the location in the cache tag memory to which the tag address of the request has been stored upon receipt of the first untranslatable response signal from the address translation unit in respect of the request.