| 摘要 |
PURPOSE:To execute an exchange instruction at high speed by providing a state holding means which performs state transition corresponding to a specific control signal from an instruction decoder. CONSTITUTION:When the XCHG(exchange) instruction targeting for first and second registers R1, R2 is issued, the fact is stored in a flag register 13. When an instruction to perform read/write on the first register R1 (or second register R2) is issued in such state, the set content of the flag register 13 is affected on the decoding condition of the read/write instruction of the first or second register. Instruction decoding is performed as if the instruction is the read/write instruction of the register which becomes the exchange opponent of the register designated by the said instruction, and the register which becomes the exchange opponent is generated. As a result, the XCHG instruction can be executed without moving data actually. Thereby, the XCHG instruction can be performed in one cycle, and also, it is performed at high speed. |
