发明名称 DELTALOG DATA GENERATING CIRCUIT
摘要 <p>PURPOSE:To obtain DELTAlog X of required interpolation data in accordance with the magnitude of X by using a small-capacity LUT to perform logarithmic conversion of X data. CONSTITUTION:A priority encoder 13 detects the most significant bit of bits '1' from data X7 to X4 of inputted upper four-bit XH and outputs SFT where this bit is '1' and the other bits are '0'. A shift register A14 loads the inputted SFT and outputs the inverted value of the least significant bit from a carry-out terminal CO to an AND gate 15 at each time of clock input. An 8-bit shift register 12 stores 8-bit X data consisting of inputted upper four bits X7 to X4 and lower bits X3 to X0; and while the carry signal is '1', data is right shifted by a shift clock 1 to perform the next operation. An XM=X/SFT register 12 inputs lower four-bit XML of XM to an LUT 6. The LUT 6 reads out data logXML in the address XML to input it to a subtractor 21.</p>
申请公布号 JPH04137117(A) 申请公布日期 1992.05.12
申请号 JP19900259632 申请日期 1990.09.28
申请人 YOKOGAWA ELECTRIC CORP 发明人 MATSUMOTO TOMOKO
分类号 G06F1/02;G06F7/556 主分类号 G06F1/02
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