| 摘要 |
A data repacker utilizing a multiplexer, one intermediate register, two shifters, and a control for these circuits. The multiplexer output is connected to the intermediate register, which has a storage length greater than the size of data words to be repacked. The first shifter receives the output of the register, and its output can be concatenated with an input data word to form one input to the multiplexer. The output of the register is provided as another input to the multiplexer. The second shifter also receives the output of the multiplexer, and has an output which is the repacker output. Information representing the number of bits in and the number of bits out is used to determine the most and least significant bits of the intermediate data which will be stored in the intermediate register, and to control the shifters.
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