发明名称 MULTI-CPU SYSTEM
摘要 <p>PURPOSE:To make a recovery instantaneously after a clock stops by sending out a clock validity signal which determines priority according to the insertion position of each CPU and also sending out the clock signal based upon the signal. CONSTITUTION:Clock generating circuits 100, 200, and 300 are added to respective CPUs 10, 20, and 30. When the clock from the clock generating circuit 100 added to the host CPU 10 stops, the stop detecting circuit 202 in the clock generating circuit 200 with precedent priority detects that and sends a clock out as a substitute for the clock generating circuit 100 with the top priority under the control of a clock validity signal sending-out circuit 203 which controls the transmission of the clock signal following the priority order. Consequently, the instantaneous recovery can be made after the clock stops without any waiting time.</p>
申请公布号 JPH04135268(A) 申请公布日期 1992.05.08
申请号 JP19900206584 申请日期 1990.08.03
申请人 MITSUBISHI ELECTRIC CORP 发明人 OMORI TADASHI
分类号 G06F15/16;G06F1/04;G06F15/177 主分类号 G06F15/16
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