发明名称
摘要 <p>PURPOSE:To eliminate deterioration in reproduced picture quality by inserting a synchronous protection circuit in between a gate signal demodulation circuit at the reception side and a counter circuit of the reception side to prevent generation of synchronous error due to noise. CONSTITUTION:The synchronous protection circuit 23 is inserted in between the gate signal demodulation circuit 18 at the reception side and the counter circuit 21 at the reception side, a waveform shaping circuit 24 of the circuit 23 waveform-shape a gate signal Gm and an output of the circuit 24 controls a counter 25. An output of the counter 25 is fed to a matrix circuit 26, from which a pulse Tp initializing the counter 21 at the reception side of the reception side clock frequency control circuit is generated. An output of the counter 21 controls a gage signal generation logic circuit 27 to generate a gate signal Gr relating to the counter 31 and the signal is fed to the circuit 24. Then the circuit 24 connects missing generated in the mark space of the gate signal Gm so as to eliminate a thin noise generated in the space period of the gate signal Gr from the counter 25 and the circuit 26.</p>
申请公布号 JPH0426257(B2) 申请公布日期 1992.05.06
申请号 JP19840245417 申请日期 1984.11.20
申请人 SANYO ELECTRIC CO 发明人 YAMASHITA AKIHIKO;SUGIURA YOJI
分类号 H04K1/06;H04L7/08;H04L9/12 主分类号 H04K1/06
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