| 摘要 |
An architecture for a digital-to-analog converter or an analog-to-digital converter comprises a segmented voltage divider comprising a first resistive voltage divider providing a multiplicity of equal selectable voltage segments any one of which may be coupled directly across a second resistive voltage divider. The loading of the first resistive voltage divider by the second voltage divider is compensated by means of a controlled current source which responds to one of the voltage segments to provide a current which may be coupled by way of current mirrors in parallel with the second voltage divider.
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