| 摘要 |
A global reset circuit especially suitable for integration into a microprocessor and implemented in CMOS technology is disclosed herein. This circuit includes reset circuitry having an input adapted for connection with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output adapted for connection with at least one circuit component to be reset, for example certain components forming part of a microprocessor. To this end, the circuitry provides a reset signal at its output upon initiation of the power supply voltage and until the power supply voltage reaches a predetermined level, at which time the reset signal is removed. A latching circuit which forms part of the reset circuitry is operated by the power supply voltage in a first state during the presence of the reset signal and in a second, latched state for removing the reset signal. The latching circuit operates in its second, latched state so long as the supply voltage remains above the predetermined level. Means also forming part of the reset circuitry is provided for grounding the latching circuit through a predetermined resistance.
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