| 摘要 |
The circuit includes a host connecting means (1) connected to a system bus (17) so as for a CPU to be able to control the operation of the input/output device. A mode control signal generating means (2) generates various mode control signals, and a phase locked loop (PLL) circuit (4) generates a frequency of 384 times the horizontal synchronizing signal. An analogue/digital converter (9) converts analogue signals to digital signals, and a data buffering means (13) transmits and receives information data to and from a picture data storing memory. A multiplexer (12) is connected to the analogue/digital converter (9), to the data buffering means (13), and to the mode control signal generating circuit (2). The circuit provides an improved picture quality.
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