| 摘要 |
Tester for dynamic testing of digital modules, containing many identical testing channels and many analytical probe channels cooperating with a controlling computer, while each of the testing channels contains a shifting register cooperating with a transmitter and a comparator cooperating with the memory of the testing signals, and each of the analytical probe channels contains the memory of the analysed signals cooperating with a shifting register and sum memory cooperating with a sum counter, characterized in that the data outputs (d11-d1n,...,dk1-dkn) of the testing signal memory (PT1-PTk) are connected to the data inputs of the shifting registers (RD1-RDk), and the serial outputs (w1-wk) of those registers are connected to the inputs of transmitters (ND1-NDk) and to the reference inputs (wo) of the comparators (K1-Kk), while the outputs of the transmitters (ND1-NDk) are connected to the terminals (b1-bk) of the tested module and to the signal inputs (ws) of the comparators (K1-Kk), and the outputs of these comparators are connected to the inputs (sk1-skk) of the control circuit (US), and also the timer input (wz) of the shifting registers (RD1-RDk) and (RA1-RAk) and the input of a frequency divider (D) are connected to the output of a timer generator (G), whose programming inputs are connected to the interface circuit (UI) and to the circuit........<IMAGE>
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