VERFAHREN ZUM QUERSTROMFREIEN BETREIBEN EINER GEGENTAKTSCHALTUNG UND ANORDNUNG ZUR DURCHFUEHRUNG DES VERFAHRENS.

摘要

The circuit has an output stage with 2 series output transistors (T1, T2) of complementary type, controlled via 2 counter-clock signals obtained from an input signal, with a time separation between their signal flanks. The output currents of the output transistors (T1, T2) are detected to allow the control counter-clock signal (U1, U2) for one output signal (T1, T2) only to be supplied when the output current of the complementary transistor (T2, T1) has dropped below a min value. Pref. the base/emitter voltages (UBE1, UBE2) of the complementary transistors (T1, T2) are compared with respective reference voltages UR1, UR2).