| 摘要 |
<p>An input buffer circuit having a latching function controlled by a transition detection circuit is disclosed. The input stage of the input buffer is connected to a delay stage, and to a transition detection circuit. The output of the delay stage is connected to a pass gate, which is controlled by the output of the transition detection circuit; a latch is connected to the other side of the pass gate. The transition detection circuit produces a pulse responsive to a transition, and the pass gate is turned off during the length of the pulse, with the latch maintaining and presenting the state of the input prior to the transition. After the pulse is complete, the new value of the input signal is latched and presented to the circuit. Since the pass gate is turned off during the transition detection pulse, a short and spurious transition at the input terminal is isolated from the latch by the pass gate (with the transition detection pulse lengthened), and does not appear at the output of the input buffer circuit. <IMAGE></p> |
