| 摘要 |
<p>A tristate output driver circuit (30, 40, 50) includes first (Q7) and second (Q8) switches for selectively connecting a logic high voltage source (VH) or a logic low voltage source (VL) to an output terminal (12) in a first, connected mode. Control nodes (14, 16) on the first and second switches (Q7, Q8) are energized in a precise, symmetrical manner to prevent multiple slopes in the output waveform by a precision input stage (31) that includes cascode outputs (Q17, Q18), cascode current sources (Q19-Q20, Q21-Q22) and bootstrapped current sources (32, 34). In a second, tristate mode, the output terminal (12) is electrically isolated from the logic high (VH) and logic low voltage sources (VL). In the tristate mode, the off-switch remains off and the on-switch is turned off by the precision input stage (31) to minimize glitches in the output waveform. A voltage clamping circuit (41, 43) clamps the control nodes (14, 16) of the switches (Q7, Q8) to a voltage more negative than a termination voltage source (Vterm), the logic low voltage source (VL), or the logic high voltage source (VH) in order that the electrical isolation of the tristate mode is maintained regardless of the value of the termination voltage (Vterm). <IMAGE></p> |
