| 摘要 |
PURPOSE:To attain the effective merger of sub-circuits by changing a circuit with all FFs and all output pins defined as the virtual output of a composite circuit, applying the clocks for each of clock phases of all output points FF of the changed circuit, and performing a test while repeating the recovery of value of the input point FFs which are destroyed by the clocks. CONSTITUTION:An original circuit is reconstructed into a composite circuit (sub-circuit) with a flip-flop (FF) group having a scan-in operation for generation of the check series regarded as a virtual input terminal and an FF group having a scan-out operation regarded as a virtual output terminal respectively. Under such conditions, the FF output point cones defining only the clock phases different from the clock phase of an output point FF as the input point FFs are merged with each other. Therefore no unknown data is generated to the input point FFs caused by the clocks when the data are fetched to the output point FFs with application of the clocks. Furthermore the scan-in value to be given to the input point FF is kept correct even in a clock application state and no malfunction is produced. Thus it is possible to effectively merge the sub- circuits without giving any change to the existing logic. |
