| 摘要 |
<p>1277333 Semi-conductor devices GENERAL MOTORS CORP 16 July 1970 [31 July 1969] 34517/70 Heading H1K A silicon planar PNP transistor comprises a P-type wafer 12 having one surface 14 with a refractory oxide coating overlain by aluminium contacts 20, 22. Within the wafer are surface extending conductivity regions; an N-type base 24; a P-type emitter 26 and a P+ expanded guard ring 28; the collector being the remainder of the wafer to define a collector base PN junction 32 and an emitter base PN junction 34. The base 24 is surrounded by a narrow collector border 36, and guard ring 28 surrounds base 24 non-contiguously and border 36 contiguously; extending to the periphery of surface 14 with inserted semi-circular collector islands 38, 40 spacedly adjacent from opposite sides of border 36. A thick layer 42 of silicon oxide overlays islands 38, 40 and border 36 while a thin layer 44 of oxide overlays guard ring 28 and a portion of emitter 26, and an intermediate thickness oxide coating overlap the base-emitter junction. Contacts 20, 22 are electrically connected to emitter 26 and base 24 and comprise bonding pads 48, 50 overlying islands 38, 40 with inwardly-extending interdigitated electrodes 49, 51 engaging base and emitter through openings of the oxide, and wire connectors 52, 54 are pressure bonded to pads 48, 50. In manufacture, surface 12 is cleaned and oxidized, a window etched therein for N-type diffusion to form base 24; reoxidized and etched to form a further smaller window overlying the base for P-type diffusion for the emitter 26. Oxide is also removed from the surface from border 32 to the perimeter except for the overlying islands 38, 40 to allow diffusion to form P + guard ring 28, followed by further oxidation. Openings in the oxide overlying emitter 26 and base 24 are etched for contacts, and aluminium contacts 20, 22 evaporated on with interdigitated electrodes connecting to base and emitter.</p> |
