| 摘要 |
PURPOSE:To lessen a vertical field effect transistor in gate threshold voltage by a method wherein a base region under a gate insulating film is lessened in surface impurity concentration. CONSTITUTION:When a P<+>-type source region 4 is formed, a thin oxide film 11 is formed on the surface of a gate electrode 6, and then boron ions are implanted using a resist 12 formed so as to provide a window to the P<+>-type source region an 4 and a gate electrode 6 as a mask. At this point, the gate electrode 6 is set high in resistivity before the implantation of ions and turned into a P-type by the implanted boron ions. Injected boron in the gate electrode 6 is diffused only near the surface of a semiconductor substrate penetrating the gate oxide film 5 to form a shallow boron diffusion layer 10 there. By this setup, a part of the N-type base region 3 under the gate oxide film 5 high in carrier concentration is compensated by the baron diffusion layer 10 as shown by a broken line, so that the N-type base region 3 can be lessened in concentration peak. By this setup, a field effect transistor of this design can be protected against punch-through and lessened in threshold voltage. |
