发明名称 |
Passive processor communications interface |
摘要 |
A passive interface between a processor and a peripheral device is shown. The peripheral device could also be another processor. The interface allows asynchronous communication between the devices. Speed limitations are minimized as the processor has the ability within the interface to know when it can send data, and when it has received data. The number of interface pins is also minimized. Also, communication between devices can still be performed even if the devices have different data bus widths.
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申请公布号 |
US5109494(A) |
申请公布日期 |
1992.04.28 |
申请号 |
US19900541446 |
申请日期 |
1990.06.22 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
EHLIG, PETER N.;PETERS, ROGER W. |
分类号 |
G01R31/3185;G06F11/267;G06F11/36;G06F13/12 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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