发明名称 RAM TYPE DSP CIRCUIT
摘要 PURPOSE:To simplify the circuit and to simplify the instruction system by allowing a RAM to have a function of a register and unifying them. CONSTITUTION:Writing in a RAM cell 20 is executed based on an address signal ADD and a control signal ASEL from a control part 1 and a control signal ISEL to an input selector 23, and data from an input latch 25 or a computing element 3 is written in a necessary address of the RAM cell 20. Also, reading-out from the RAM cell 20 is executed based on the address signal ADD and the control signal ASEL from the control part 1 and a control signal OSEL to an output selector 24, and data from the RAM cell 20 is latched to one of output latches 26 - 29, and outputted to the computing element 3 or the outside. In such a way, the circuit is simplified and the instruction system is simplified.
申请公布号 JPH04127365(A) 申请公布日期 1992.04.28
申请号 JP19900249135 申请日期 1990.09.19
申请人 FUJITSU LTD 发明人 HASEGAWA KENZO
分类号 G06F7/00;G06F17/10 主分类号 G06F7/00
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