A METHOD FOR CONSTRUCTING BP-BUS

摘要

Synchronizing clock pulses are generated by a central slot (12) so as to be supplied through signal lines of a back plane (11). Two outer slots (13)(14) and (15)(16) which are adjacent to each other, and which are located outwardly from the central slot (12) are electrically bundled together as groups. The lengths of the signal lines of the back plane (11), which connect the groups to the central slot (12), are made to be the same, so that bus clocks of the central slot (12) should reach the groups simultaneously. The method simplifys the circuit constitution, to facilitate a serial termination, and minimizes the load of the signal receiving end.