TRIGGER CONTROL LOGIC

摘要

The logic includes first and second general control registers (GCR0) (GCR1) for receiving processor data. NOR gates (N1)-(N4) receive bus approval signals and bus approval enable signals from the first general control register (GCR0). OR gates (O1)-(O4) receive the output signals of the NOR gates (N1)-(N4), and also receive a bus approval enable signal from the second general control register (GCR1). A programmable logic array (PLA) receives other enable and disable signals, and the output of the programmable logic array (PLA) is supplied to an input terminal (D) of a DF/F. The logic simplifies its circuit, while reinforcing its functions.