| 摘要 |
PURPOSE:To facilitate the contacts between wiring layers and active regions while decreasing the step difference peculiar to the multilayer wiring structure by filling up element separating regions with respective one wiring layer. CONSTITUTION:The element separating regions wherein the first trenches are made inward from the main surface of a p-type semiconductor substrate 1 to be filled up with an insulator 2 as well as the wiring comprising the second trenches narrower and shallower than the first trenches to be filled up with a conductor in the element separating regions are formed. Next, bit lines and contact holes are arranged in the small area having the least useless space so that a laminated cell forming word lines and the bit lines and having an underneath layer in the least ruggedness to form a laminated layer capacitor may be structured beneath the laminated layer capacitor. Through these procedures, this structure can be formed in high flatness. |
