发明名称 MULTIPLIER
摘要 PURPOSE:To curtail the quantity of a hardware required for extending a code by generating a code and an extension code of a multiplicand inputted to a multi-input adder by a selecting signal from a decode of a booth and a code of an original multiplicand. CONSTITUTION:(n) pieces of decoders 1 fetch bits of a multiplier by three bits each and output a code (+ or -) conforming to an algorithm of a booth and an X0,X1,X2 instructing signal. (n) pieces of selectors 2 receive the code (+ or -) and the X0,X1,X2 instructing signal from these decoders 1, and generate a code and an extension code of a multiplicand. Also, the selector 2 is constituted so that the lower digit is shifted ot the right by two bits each from its upper digit. That is, the code and the extension code of the multiplicand inputted to the selector 2 are generated by a selecting signal (code+ or -and X0,X1,X2) given from a decoder 2 of the booth and a code of an original multiplicand X. In such a way, the quantity of a hardware required for extending the code can be curtailed.
申请公布号 JPH04123129(A) 申请公布日期 1992.04.23
申请号 JP19900243142 申请日期 1990.09.13
申请人 FUJITSU LTD 发明人 MIYAMOTO KIYOBUMI
分类号 G06F7/533;G06F7/52;G06F7/527;G06F7/53 主分类号 G06F7/533
代理机构 代理人
主权项
地址