Frame alignment circuit.

摘要

A frame alignment circuit is disclosed which includes multi-stage dividing counters and multi-stage line demultiplexing circuits. The shift pulse for frame synchronizing is converted to the width of the first divided clock signal and applied to the first dividing counter. Accordingly, the frame synchronization is easily established by demultiplexing the high rate multiplexed coded signal even if the number of demultiplexing line is increased.