| 摘要 |
<p>A delay circuit wherein MOS transistors (21, 22) for resistors for controlling the delay time of a CMOS inverter (26) are inserted between the source of the CMOS inverter (26) and power supply potentials (GND, Vdd) respectively and the respective sources of the MOS transistors (21, 22) are connected with the power supply potentials (GND, Vdd) respectively. Therefore, by changing the drain currents of the MOS transistors (21, 22) the control voltages (Vn, Vp) thereof are changed respectively. The driving capability of the CMOS inverter (26) is consequently changed, allowing the delay time of the inverter (26) to be regulated. Further, since the sources of the MOS transistors (21, 22) are connected with the power supply potentials (fixed potentials) (GND, Vdd) respectively, the delay time being stable even against disturbance is obtained.</p> |
