PLL frequency synthesizer.

摘要

A PLL frequency synthesizer includes a reset circuit (29) which determines whether or not an oscillator (21) starts to normally generate an oscillation signal in response to a power save signal which intermittently operates the oscillator in a standby mode and which outputs a reset signal to a prescaler (24) when it is determined that the oscillator normally generates the oscillation signal. A hold circuit (30) prevents a frequency-divided signal from the prescaler to a programmable counter (26) and an initial phase detection circuit (31) until the prescaler is reset to an initial state in response to the reset signal and starts to normally generate the frequency-divided signal. <IMAGE>