Method and apparatus for testing a VLSI device.

摘要

A method and apparatus for testing a VLSI device 10 are described. The invention uses the idea that the internal logic of the VLSI device can be broken down into linked sections or cones. Thus, after completing the test of all the logic gates 110, 120 in one cone of the device 10, it will not be necessary to retest those gates 120 which overlap into other cones. Hence, some of the bit values placed on the input latches 30 to the device 10 are irrelevant to the test. The apparatus incorporates a Linear Feedback Shift Register (300) which is fed by a seed to produce a bit pattern to test the VLSI device (10). The seed is so chosen that the LFSR generates the required bit values on the input latches 30 which are required for the particular test being carried out and pseudo-random values for all other latches.