| 摘要 |
<p>A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor (T3) which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors (T1, T2) are reverse biased or clamped to zero to prevent any leakage paths. The N-well biasing transistor (T3) is connected between an input/output pad (152) and a pair of CMOS final drive transistors (T1, T2); the pair of CMOS final drive transistors (T1, T2) connected to a precharge CMOS circuit (T8, T9, 158, 160, 162, 164) having an input and output, the final drive transistors (T1, T2) providing amplification of the precharge CMOS circiut output; a pad signal (150) electronically connected to the input of the precharge CMOS drive circuit (T8, T9, 158, 160, 162, 164) and to a tri-state enable (154, 156), the tri-state enable selecting the active state of the input/output pad (152); whereby the biasing transistor (T3) biases the N-well to effectively prevent any leakage current when the circuit is in an unpowered state. <IMAGE></p> |
