| 摘要 |
PURPOSE:To minimize the scale of an ELC circuit requiring much power consumption by shifting bits after serial/parallel conversion so as to detect a frame pattern. CONSTITUTION:A serial/parallel conversion means 31 receiving a serial digital signal whose frequency is (f) converts the signal into an n-bit parallel signal, a register 41 fetches an output of the conversion means 31 for each of f/n clock and revises its latch content into a new n-bit reception signal. A frame check means 61 compares a pulse train resulting from fetching a bit of a specific order of an output of a data shift means 51 at a prescribed period with a specific frame pulse pattern. When the frame check means 61 discriminates dissidence, the means 61 generates a control signal to shift one bit only and it is fed to a shift signal generating means 71. Thus, the shift circuit is formed by a circuit of a low speed and small power consumption employing a CMOS or the like. |
