发明名称 ARRANGEMENT FOR SIMULTANEOUSLY DEALING WITH TRANSFER REQUESTS PRODUCED BY CENTRAL, ARITHMETIC AND INPUT-OUTPUT PROCESSORS OF A SUPER COMPUTER
摘要 For transfer of memory contents between an extended buffer memory and one of a first and a second main memory and of a peripheral storage device connected to an input-output processor, a transfer controlling arrangement can simultaneously receive transfer requests produced by a central processor, an arithmetic processor, and the input-output processor and can control the transfer requests. The transfer controlling arrangement comprises an extended buffer memory transfer controller connected to the central and the input-output processors through a first transfer controller, to the arithmetic processor through a second transfer controller, and to the extended buffer memory.
申请公布号 US5107416(A) 申请公布日期 1992.04.21
申请号 US19880290623 申请日期 1988.12.27
申请人 NEC CORPORATION 发明人 JIPPO, AKIRA;OKAMOTO, MASAFUMI;OKANO, TADASHI
分类号 G06F13/12;G06F13/28 主分类号 G06F13/12
代理机构 代理人
主权项
地址