| 摘要 |
PURPOSE:To enable a delay circuit to be constituted without increasing an area of a master-slice system integrated circuit device by connecting a capacitor to a VSS-side power supply wiring and a signal wiring. CONSTITUTION:A first-layer metal wire 102 and a second-layer metal wire 103 are placed below a pad electrode opening 104 sandwiching an electrically insulated film for constituting a first capacitor and a second-layer metal wire 103 and a master-slice system integrated-circuit device substrate are placed sandwiching the electrically insulated film, thus constituting a second capacitor. An output of a logic circuit element 311 is connected to an input of a logic circuit element 312 and a signal wire connection terminal of a delay cell 306. A wiring position of a delay cell 306 is placed within an I/O cell wiring region where no I/O cell 307 is placed, a signal wire 310 is electrically connected to a signal wire connection terminal, and a VSS side power supply wire 305 is electrically connected to a power supply wire connection terminal. |
