| 摘要 |
PURPOSE:To obtain a cell phase synchronizing circuit with very less buffer capacity and small delay time by inserting an idle cell or deleting an idle cell so as to adjust a frequency phase fluctuation. CONSTITUTION:A cell synchronization section 12 detects a border between cells of an input signal series. Upon the receipt of the result of the synchronization section 12, a cell type detection section 17 detects a type of a cell such as valid or invalid cell or a cell with high or low priority based on a header of a cell or the like. A write control section 13 applies write control to an elastic store 11a. An output of the synchronization section 12 is inputted to the control section 13, which uses it as information to give a write head position of the store 11a. An input signal series is written in the store 11a by a same clock signal (or address information) from the control section 13. Moreover, a same read reset clock signal indicating a head of a cell between plural transmission lines is given to a read side and the phase of cells between the plural transmission lines are matched. |
