发明名称 EMULATOR CIRCUIT
摘要 PURPOSE:To completely know the executing state of a processor by adding a read-out count setting circuit provided with an instruction byte number storage part and a counter so that consecutive instructions beginning from a first operation code can be read out of a queue. CONSTITUTION:A read-out count setting circuit 11 provided with an instruction byte number storage part 13 for outputting a prescribed value in accordance with how many byte instruction an instruction beginning from a first operation code is when a first operation code of an instruction of a processor 2 is inputted, and a counter 15 for setting this output value and executing the count is added. In such a state, when a queue status signal 33 is received, a first operation code is read out of a first-in first-out storage device 4 and inputted to a number of instruction bytes storage part 13, and thereafter, until the count of the counter 15 comes to a prescribed value, the contents of the first-in first-out storage device 4 are read out, and consecutive instructions beginning with a first opera tion code are read out. In such a way, in the case of executing instruction tracking of the processor, dequeuing can be executed, and a correct analysis can be executed.
申请公布号 JPH04118725(A) 申请公布日期 1992.04.20
申请号 JP19900238203 申请日期 1990.09.08
申请人 YOKOGAWA HEWLETT PACKARD LTD 发明人 FUKAZAWA MASAYUKI
分类号 G01R31/317;G06F9/32;G06F11/22 主分类号 G01R31/317
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