发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To allow efficient wiring by CAD by providing two lines of terminals whose positions in the height direction are the same as the terminals of other cells and providing wiring (WL, WL') which connects polycells in the area between the two terminal lines. CONSTITUTION:A unit block 20 has a height which is even in the Y direction and is composed of polycells 20a, 20b... whose widths in the X direction are different. The polycells are commonly provided with a source conductive body 201 in the X direction along the top side and a second power source conductive body 202 in the Y direction along the bottom side. For block 20, input/output terminals are arranged at the fixed height in the Y direction to form terminal lines C1 and C2. A wiring area WR is formed between the lines, and wiring conductive patterns WL, WL', etc., are formed in the wiring area WR being connected with the terminals 23.
申请公布号 JPH04116951(A) 申请公布日期 1992.04.17
申请号 JP19900237721 申请日期 1990.09.07
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 TANIZAWA SATORU;TOKUDA HIDEO;ICHINOSE SHIGENORI;HIROCHI KATSUJI;DOI TAKEHITO
分类号 H01L21/82;G06F17/50;H01L23/528;H01L27/02 主分类号 H01L21/82
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