发明名称 PARALLEL MULTIPLEX INVERTER
摘要 PURPOSE:To simplify the control circuit, to suppress ripple in output current and to ensure follow-up performance by performing current follow-up control of two inverters and correcting the hysteresis width of one inverter equivalently when the difference between a current command and the output current of inverter deviates from a predetermined range. CONSTITUTION:Three-phase voltage type inverters 1, 2 are connected, respectively, through reactors 81, 82 with a load 4 terminal. When the sum of detection currents ia1, ia2 deviates remarkably, in positive or negative side, from a current command ia*, 1 is outputted from a three-level comparator 132 and the input to a hysteresis comparator 121 is subjected to incremental/decremental correction through a coefficient unit 132. Consequently, when current ripples of both inverters 1, 2 overlap, output from the hysteresis comparator 121 on the side of the inverter 1 is inverted, which is equivalent to differentiate the hysteresis width from that of a comparator 122 on the side of the inverter 2, and then the switching phases of the inverters 1, 2 are shifted thus suppressing the current ripple.
申请公布号 JPH04117137(A) 申请公布日期 1992.04.17
申请号 JP19900236184 申请日期 1990.09.06
申请人 MEIDENSHA CORP 发明人 NISHITOBA MINORU
分类号 H02J3/38;H02M7/493 主分类号 H02J3/38
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