发明名称 MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG
摘要 A method of manufacturing a semiconductor wafer, comprises depositing a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, performing a first metallization to deposit a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, performing an in-situ desorption of physically and chemically water vapour in a dry environment at a temperature of at least 400 DEG C and not more than 550 DEG C for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25 DEG C the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, etching via holes through the dielectric and spin-on glass layers to reach the tracks of the first interconnect layer, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks while maintaining the dry environment. The subsequent etching and metallization steps after the desorption step are performed without re-exposure of the wafer to ambient conditions. This technique permits the reliable use of inorganic or quasi-inorganic spin-on glasses in non batch type sputtering equipment.
申请公布号 WO9206492(A1) 申请公布日期 1992.04.16
申请号 WO1991CA00343 申请日期 1991.09.25
申请人 MITEL CORPORATION 发明人 OUELLET, LUC
分类号 H01L21/28;H01L21/314;H01L21/316;H01L21/768;H01L21/8238;H01L27/092 主分类号 H01L21/28
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