发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent latchup by setting a threshold voltage of a P-channel MOS transistor(TR) of a CMOS circuit so as to satisfy a specific condition. CONSTITUTION:When an absolute value of a threshold voltage Vthp of a P- channel MOS TR 2 is smaller than 0.7V being a forward on-voltage of the pn junction, a channel layer is formed to the TR 2 before the pn junction is conductive and a current I1 flows from a drain DP of the TR 2 to a source SP. Thus, the drain DP of the P-channel MOS TR 2 is clamped to a level Vc+ Vthp, the pn junction is not conductive thereby preventing a parasitic bipolar TR QA from being turned on. That is, since the TR QA is not turned on, no latchup is induced. Thus, the absolute value of the threshold voltage Vthp of the P-channel MOS TR 2 connecting to an external terminal is made lower than the voltage 0.7V where the pn junction is conductive in the wafer process stage to prevent easily latchup.
申请公布号 JPH04115718(A) 申请公布日期 1992.04.16
申请号 JP19900236313 申请日期 1990.09.06
申请人 FUJITSU LTD 发明人 KOYOU KAZUTO
分类号 H03K19/003;H03K17/08;H03K19/0948 主分类号 H03K19/003
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