发明名称 HIGH-SPEED DATA PROCESSOR
摘要 PURPOSE:To reduce the generation of useless calculation due to the delay of data propagation and to shorten the time for processing by supplying the columnar data of one-dimensional or two-dimensional arrangement data to be distributed to an arbitrary processing element (PE) while shifting them. CONSTITUTION:Respective PE0-PEN-1 are equipped with timing delay means shown by 4-0 to 4-(N-1), and processing starting timing is delayed only by 0-(N-1)tau respectively. Namely, the PE0 respectively processes columnar data D00-DN-1 and 0 in respective cycles from 0 to (N-1)tau and dispatches respective processed results to the PE1. The PE1 starts the processings of the columnar data D01-DN-1,1 after being delayed by 1tau rather than the PE0 and dispatches the respective processed results to the PE2. In this way, the PEN-1 starts the processings of the columnar data D0,N-1-DN-1,N-1 after being delayed by (N-1) rather than the PE and finishes the processing in (2N-2)tau. Thus, the entire processing time becomes order OMEGA(N) of N and extremely shortened in comparison with the conventional device.
申请公布号 JPH04114262(A) 申请公布日期 1992.04.15
申请号 JP19900234772 申请日期 1990.09.05
申请人 FUJITSU LTD 发明人 SASAKI SHIGERU
分类号 G06F15/16;G06F15/80 主分类号 G06F15/16
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