| 摘要 |
<p>PURPOSE:To contrive reduction of a layout area by using N-channel Tr and P-channel Tr without using a 2-input NAND circuit. CONSTITUTION:When an address of ROM indicated by the input signals 1,2 is '00' address, a high level of high voltage source is normally inputted to the gates of a P-channel transistor (P-ch Tr) 7 and a N-ch Tr 8 to make both to be ON. An intermediate potential making the high voltage 6 to high level and the earth power source (GND) 18 to low level is inputted to the gate of a P-ch Tr 15. By means of considering the ratio of the P-ch Tr 7 and N-ch Tr 8 beforehand, the P-ch Tr 15 is made ON, and a drain of N-ch Tr 10 and gates of P-ch Tr 7, N-ch Tr 8 become high level of the high voltage sources 5,6, then the output 16 becomes high level of the high voltage source 6 and is outputted as the high level of a writing control circuit. The outputs 21,22 of non-selection addresses other than the above are in the low level. Thus, the layout area can be reduced.</p> |
